一种用于流水线模数转换器的电容失配校准方法  

A Capacitor Mismatch Calibration Technique for Pipelined A/D Conversion

作　　者：李福乐[1] 王红梅[2] 李冬梅[2] 王志华[1] 

机构地区：[1]清华大学微电子学研究所,北京100084 [2]清华大学电子工程系,北京100084

出　　处：《Journal of Semiconductors》2005年第9期1838-1842,共5页半导体学报（英文版）

基　　金：国家高技术研究发展计划(批准号:2002AA1Z1720);国家重点基础研究发展规划(批准号:G2000036508)资助项目~~

摘　　要：对于流水线模数转换器(ADC),电容失配是一种主要的非线性误差源.为了减小电容失配误差,提出了一种电容失配校准的方法.该方法通过一种电荷相加、电容交换和电荷反转移的电路技术,可将电容失配误差减小至其2次项.基于所提出的方法,设计了一种0.6μmCMOS,13b,2MS/s的流水线ADC实验芯片.对所设计的实验芯片进行测试,得到了0.5LSB的DNL和2.5LSB的INL,并且当以614kHz的采样率对19.2kHz的输入进行转换时,得到了71.2dB的SFDR和64.1dB的SNDR,当以2MHz的采样率对125kHz的输入进行转换时,得到了70.6dB的SFDR和62.22dB的SNDR.以上结果表明,ADC得到了超出电容匹配精度的线性度,证明了所采用的电容失配校准方法的有效性.A novel capacitor mismatch calibration technique for pipelined analog-to-digital conversion is presented. The nonlinear capacitor mismatch error is reduced to the second order through an algorithmic circuit method,involving charge summing, capacitors exchange, and charge redistribution. A 13b, 2Msample/s pipelined A/D converter implemented in 0. 6μm CMOS technology has been designed to verify the proposed technique. Measured performance includes 0. 5LSB of DNL, 2. 5LSB of INL, 71.2dB of SFDR and 64. ldB of SNDR for 19.2kHz input at 614k sample/s,70.6dB of SFDR and 62. 22dB of SNDR for 125kHz input at 2M sample/s. This result shows that the linearity of the ADC is better than the capacitor matching precision decided by the technology. Thus the adopted capacitor mismatch calibration technique is proved to be effective.

关 键 词：模数转换器 流水线 电容失配校准 

分 类 号：TN792[电子电信—电路与系统]