一种比特平面并行处理的零树编码结构  

A bit plane-parallel VLSI architecture for zero tree coding

作　　者：刘凯[1] 李云松[2] 吴成柯[2] 

机构地区：[1]西安电子科技大学计算机学院,陕西西安710071 [2]西安电子科技大学ISN国家重点实验室,陕西西安710071

出　　处：《电路与系统学报》2005年第5期23-26,共4页Journal of Circuits and Systems

基　　金：国防科技预研基金项目(41001030203)

摘　　要：提出了比特平面并行处理的零树编码结构。根据内嵌编码的零树结构,指出每一个比特平面的编码信息可以同时获得,从而给出了并行的零树编码结构。与现有的结构相比,该结构具有并行度高,没有中间缓冲等特点。实验结果表明,处理速度有明显提高,图像质量可满足大多数应用要求。In this paper, we present a bit plane-parallel architecture for zero tree coding which is suitable for VLSI implementation. After the structure of zero tree for embedded coding is analyzed in detail, the coding information of each bit plane for a zero tree can be obtained simultaneously. Then, the bit plane-parallel architecture for zero tree coding is proposed, and the corresponding VLSI architecture to implement the formulated requirements is presented. Compared with other architectures, it has advantages of high parallelism, and no intermediate buffer. The experimental results show that the proposed architecture upgrades the processing speed greatly compared with others. The quality of images can satisfy most application fields.

关 键 词：图像压缩 零树编码 比特平面并行 VLSI结构 

分 类 号：TN919.81[电子电信—通信与信息系统]