高速基2FFT处理器的结构设计与FPGA实现  

FPGA implementation of a high-speed base-2 256-point FFT

作　　者：李小进[1] 初建朋[1] 赖宗声[1] 徐晨[2] 景为平[2] 

机构地区：[1]华东师范大学微电子电路与系统研究所,上海200062 [2]南通大学,江苏南通226007

出　　处：《电路与系统学报》2005年第5期49-53,共5页Journal of Circuits and Systems

基　　金：上海市科委PDC资助项目(027062012;047062023);上海市AM发展研究基金(AM0403);上海市信息委(04-联专-001)

摘　　要：本文研究了采用AISC来实现高速实时基2FFT处理器的设计方案。在实现中采用了单基2定点内核,设计了防溢出控制结构,在不增加系统延时的基础上,提高了运算精度。设计了对称乒乓RAM结构,在保证蝶形运算核的占用率的条件下,提高了该FFT处理器的连续运算能力。将RAM集成在FFT处理器内部,提高了使用的灵活性。本文所设计的FFT具有可配置特性,可根据需要计算2的幂次方的FFT。256点的FFT运算只需1072个时钟周期,在VertexII-xc2v1000上综合实现,频率可达112.007MHz,完成整个256点的FFT运算仅需9.57μs。This paper provides the design method of a high speed based 2 FFT processor using FPGA and ASIC. It employs radix-2 DIT arithmetic and fixed point core. A structure of anti-overflow which enhances computing precision without reducing the performance has been designed. A symmetry ping-pang structure has been brought forward to increase the continuous computing capability of the butterfly＇ core. In order to promoting its flexibility, the RAMs have been integrated with the FFT processor. The number of processing points is configurable, which is 2^n. 1072 clock periods are needed to achieve a 256 point FFT computation. The processor has been realized with Vertexll-xc2v1000256-4 which shows that the frequency can reach 112.007MHz, and computing time is 9.57μs.

关 键 词：FFT FPGA 防溢出 对称乒乓结构 

分 类 号：TN47[电子电信—微电子学与固体电子学]