用FPGA实现互联的多DSP并行系统结构  

Parallel system architecture of multi-DSP interconnected by FPGA

作　　者：颜露新[1] 张天序[1] 邹胜[1] 钟胜[1] 

机构地区：[1]华中科技大学图像识别与人工智能研究所图像信息处理与智能控制教育部重点实验室,湖北武汉430074

出　　处：《系统工程与电子技术》2005年第10期1757-1759,1775,共4页Systems Engineering and Electronics

摘　　要：为满足实时图像处理要求,在分析了常见DSP并行系统结构基础上,提出了一种基于FPGA互联的DSP并行系统结构。该并行结构通过在FPGA内实现互联网络和特定的数据通信协议,实现三片DSP(TMS320C6713)的有效互联,系统结构可重构、可扩展。对采用该并行结构的原型系统的测试表明,DSP间数据通信既获得了较大的持续带宽又降低了传输延迟,可以满足并行实时处理要求。To meet real-time image processing demands, the paper analyses the architectures of common parallel systems and presents a DSP parallel system architecture based on FPGA, This architecture is structured with high performance DSPs interconnected by PGA, Within FPGA a FIFO interconnection network and the specific data communication protocol are implemented, which interconnect 3 DSPs（TMS320C6414） effectively, The system architecture is reconfigurable and scalable, The measured performances in the prototype with the proposed parallel architecture show high data transfer rate as well as low latency between DSPs and meet parallel real-time processing demands.

关 键 词：实时图像处理 DSP并行系统 互联网络 结构可重构 

分 类 号：TN957.51[电子电信—信号与信息处理]