低速CPU系统中高速采样与海量缓存的实现  

Realization of High Speed Sampling and Massscale Buffer Storage in Low Speed CPU

作　　者：施海宁[1] 王加俊[1] 金心明 姚建林[2] 

机构地区：[1]苏州大学电子信息学院,江苏苏州215004 [2]苏州热工研究所,江苏苏州215004

出　　处：《现代电子技术》2005年第20期42-43,46,共3页Modern Electronics Technique

摘　　要：高速数据采集在各工业领域有着广泛的应用,高速、高性能元器件价格昂贵,采购困难。在成本敏感、设计期限紧张的前提下,如何利用常见的元器件,既能满足采样速率的要求,又有较大的缓存空间,是设计人员经常遇到的问题。本文提出了一种高速采样与海量缓存的实现方法,该方法以低速器件的协调工作获得高速的采样率,并可以不受M CU速度与寻址空间的制约。根据本方法设计的电路总体工作频率不高,降低了对单个元器件性能的要求,电路的可靠性大为提高。The high speed data acquisition has a wide application in a field of all industries,while high speed and high quality elements are expensive and of difficulty in procurement. The issue which designers have came across constantly is that in the event of inadequate cost and design deadline,to meet the requirements of both samplings speed and a mass -scale buffer storage space by using common elements. This paper offers a method for realization of high speed sampling and mass -scale buffer storage result in high speed sampling rate which is coordinated by low speed apparatus ,which will not be restricted by the velocity and address space of MCU. The overall operating frequency of electrocircuits designed based on this method,whlch downs the requirement for the performance of individual elements and greatly improves the reliability of electrocircuits.

关 键 词：高速数据采集 高速缓存 海量缓存 CPLD 

分 类 号：TP333[自动化与计算机技术—计算机系统结构]