Power Efficient Sub-Array in Reconfigurable VLSI Meshes  

作　　者：Ji-Gang Wu Thambipillai Srikanthan 

机构地区：[1]Centre for High Performance Embedded Systems, School of Computer Engineering, Nanyang Technological University Singapore 639798

出　　处：《Journal of Computer Science & Technology》2005年第5期647-653,共7页计算机科学技术学报（英文版）

摘　　要：Given an m × n mesh-connected VLSI array with some faulty elements, the reconfiguration problem is to find a maximum-sized fault-free sub-array under the row and column rerouting scheme. This problem has already been shown to be NP-complete. In this paper, new techniques are proposed, based on heuristic strategy, to minimize the number of switches required for the power efficient sub-array. Our algorithm shows that notable improvements in the reduction of the number of long interconnects could be realized in linear time and without sacrificing on the size of the sub-array. Simulations based on several random and clustered fault scenarios clearly reveal the superiority of the proposed techniques.Given an m × n mesh-connected VLSI array with some faulty elements, the reconfiguration problem is to find a maximum-sized fault-free sub-array under the row and column rerouting scheme. This problem has already been shown to be NP-complete. In this paper, new techniques are proposed, based on heuristic strategy, to minimize the number of switches required for the power efficient sub-array. Our algorithm shows that notable improvements in the reduction of the number of long interconnects could be realized in linear time and without sacrificing on the size of the sub-array. Simulations based on several random and clustered fault scenarios clearly reveal the superiority of the proposed techniques.

关 键 词：degradable VLSI mesh RECONFIGURATION heuristic algorithm FAULT-TOLERANCE NP-COMPLETE 

分 类 号：TN47[电子电信—微电子学与固体电子学]