异步串行通信下位机的FPGA设计与实现  

The FPGA Design and Development of the Under Levels Computer in Asynchronous Serial Communication

作　　者：孟繁智[1] 

机构地区：[1]国防科技大学电子科学与工程学院卫星导航定位研发中心,长沙410073

出　　处：《微处理机》2005年第5期94-96,共3页Microprocessors

摘　　要：本文介绍了如何使用FPGA来设计异步串行通信中的下位机,重点分析了FPGA中接收模块的设计要点,并且给出了仿真的时序图;同时给出了一种帧通信协议,介绍了微控制器软核PicoB laze进行协议解释的处理流程。本文设计的异步通信模块在实际系统中运行稳定可靠,证明了设计方案的正确性。This paper presents how to use the FPGA to design the under levels computer in asynchronous serial communication, and focuses on the key design points of the receiving module in FPGA , together with the simulated timing graphs ; This paper also provides a type of frame communication protocol and the processing flow of the soft microcontroller core PicoBlaze to translate the protocol. The asynchronous serial communication module designed in this paper is running stably and reliably in the real system, which proves the correctness of this paper.

关 键 词：异步串行通信 现场可编程门阵列 微控制器 

分 类 号：TN402[电子电信—微电子学与固体电子学]