高速网络TCP/IP减荷的研究  

Research about TCP/IP Offloading in High Speed Network

作　　者：颜永红[1] 张帆[1] 严志康[1] 

机构地区：[1]湖南大学,湖南长沙410082

出　　处：《现代电子技术》2005年第22期31-33,36,共4页Modern Electronics Technique

摘　　要：近十年来,随着网络技术的发展,网络带宽迅速增长,而同期CPU的性能未得到相应的提高。在吉比特网络下,网络终端CPU处理TCP/IP协议的能力已经成为限制网络应用的瓶颈。为了使终端用户能充分利用广阔的带宽资源,需要提高网络终端的协议处理能力。文中基于FPGA的硬件设计,将原来由软件完成的IP层协议功能完全卸载出来,向CPU提供硬件支持。并且通过功能仿真、综合后仿真、布局布线后仿真验证了设计的可行性,由静态时序分析可知,协议处理器的时钟频率可达50 MH z,处理IP数据流的能力可以达到1.6 G b/s的网络线速度。In the past ten years, with the development of network technology, the bandwidth of the network is increased rapidly. And in the corresponding period ,the performance of CPU has not got the corresponding improvement. Over Gigabit Ethernet, the power of terminal CPU to process TCP/IP stacks has already became the bottleneck which has limited network application. In order that the end-user can take advantage of the vast band resource ,it＇s necessary to improve the ability of processing protocols in terminal system. In this paper the total tasks involved in IP layer which are traditionally processed in software are offloaded by the hardware designing based on FPGA to provide hardware support to microprocessor. The feasibility of the design has been proved by functional simulation,post-synthesis simulation and post -place＆route simulation. It is known by static timing analysis, the clock frequency of the protocol processor may attain 50 MHz and the ability of processing IP-stream achieves the 1.6 Gb/s network＇s wire-speed.

关 键 词：吉比特网络 终端 卸载 仿真 协议处理器 

分 类 号：TP393.03[自动化与计算机技术—计算机应用技术]