用Verilog-HDL设计序列检测器  

Design a Sequence-inspected Equipment in Verilog-HDL

作　　者：鄢靖丰[1] 陈晓黎[2] 王平[1] 

机构地区：[1]中国地质大学计算机学院,武汉430074 [2]湖北广播电视大学,武汉430074

出　　处：《计算机与数字工程》2005年第11期118-121,共4页Computer & Digital Engineering

摘　　要：简要介绍Verilog-HDL设计数字电路基本原理,并用它具体的设计一个序列检测器,且与传统的用J-K触发器所设计的检测器进行了比较,最后在Synplify开发环境进行仿真综合,自动生成了满足给定条件的序列检测器物理电路。In this paper, Verilog-HDL（a hardware description language） is introduced, and how to design digital circuit？ A sequence- inspected equipment is designed in Vexilog- HDL, and is compared with traditional one with J - K trigger, and is synthesized and emulated in Synplify. It can be obtained sequence- inspected equipment automatically as expected.

关 键 词：VERILOG-HDL SYNPLIFY 电子设计自动化 序列检测器 

分 类 号：TN79[电子电信—电路与系统]