多值低功耗双边沿触发器设计  

Design of low power multivalued double-edge-triggered flip-flop

作　　者：胡俊锋[1] 沈继忠[1] 姚茂群[1] 王柏祥[1] 

机构地区：[1]浙江大学信息与电子工程学系,浙江杭州310028

出　　处：《浙江大学学报（工学版）》2005年第11期1699-1702,共4页Journal of Zhejiang University：Engineering Science

基　　金：浙江省自然科学基金资助项目(Y104368)

摘　　要：通过分析现有基于二值时钟的二值双边沿触发器的设计思想,设计了基于二值时钟的三值双边沿触发器.进一步利用多值时钟的多个跳变沿设计了基于三值时钟的三值双边沿触发器,充分利用了多值信号携带信息量大的优点,设计的三值双边沿触发器结构简单.模拟结果表明,设计的三值双边沿触发器具有正确的逻辑功能,并可以大幅降低功耗.By analyzing the design method of the binary double-edge-triggered flip-flop based on binary clock, a ternary double-edge-triggered flip-flop based on binary clock was proposed. Then taking advantage of multivalued clock＇s multiple triggered edge, a ternary double-edge-triggered flip-flop based on ternary clock was designed. For using multivalued signals can increase the information-carrying capacity, the structure of the designed ternary double-edge-triggered flip-flop circuit becomes simpler. Simulation result shows that the designed ternary double-edge-triggered flip-flop has correct logic function and relatively lower power consumption.

关 键 词：低功耗 双边沿触发器 多值逻辑 三值时钟 

分 类 号：TN432[电子电信—微电子学与固体电子学]