MPEG-4运动补偿的亚像素内插过程及其硬件实现  

Sub-pixel interpolation of MPEG-4 motion compensation and its hardware implementation

作　　者：姚栋[1] 虞露[1] 

机构地区：[1]浙江大学信息与通信工程研究所,浙江杭州310027

出　　处：《浙江大学学报（工学版）》2005年第11期1703-1707,共5页Journal of Zhejiang University：Engineering Science

基　　金：国家自然科学基金资助项目(90207005);国家"863"高技术研究发展计划资助项目(2002AA1Z1400)

摘　　要：对MPEG-4视频解码标准中运动补偿的亚像素内插过程作了算法介绍,基于算法提出了一种1/4像素精度内插的硬件结构设计,包括整个内插过程内部的子模块功能划分、设计内部的数据交互存储以及主要运算部件的优化等,并对其内部核心计算部件八抽头FIR滤波器作了详细的结构介绍.采用基于现场可编程门阵列(FPGA)的验证方法,整个设计在54 MHz时钟频率下可以实时完成格式为CCIR的图像内插过程,并给出了在ASIC设计工具下的综合规模(在2万门左右).最后从算法和实现两个不同角度提出了内插过程的扩展建议.The sub-pixel interpolation algorithm of motion compensation in the video coding standard MPEG-4 was introduced. Based on this algorithm, a new hardware structure of quarter-pixel interpolation including sub-module division, internal data interaction and storage and optimization of the kernel arithmetic unit was proposed. The structure of the kernel arithmetic unit with 8-taps FIR filter was introduced in detail. With the FPGA-based verification method, the design could realize the interpolation of pictures with CCIR format in system frequency of 54 MHz. The ASIC hardware scale was about 20 000 gates （without the memory）. Some suggestions on the theoretical and practical extension of interpolation process were also offered.

关 键 词：MPEG-4 运动补偿 内插 1/4像素 ASIC 

分 类 号：TN492[电子电信—微电子学与固体电子学]