混合模块无等待时间序列超前进位加法器设计  

Design of Hybrid Modules Cascade Carry Lookahead Adders without Waiting Time Sequence

作　　者：王元媛[1] 王礼平[2] 

机构地区：[1]厦门大学数学科学学院,福建厦门361005 [2]中南民族大学电子信息工程学院,湖北武汉430074

出　　处：《微电子学与计算机》2005年第12期12-15,20,共5页Microelectronics & Computer

摘　　要：在不增加超前进位加法器模块延迟时间的条件下,为最大限度地扩展操作位数,在分析混合模块超前进位加法器(CLA)延迟时间公式的基础上提出了混合模块无等待时间序列超前进位加法器。给出了混合模块CLA的无等待时间序列和无等待时间完全序列的定义,推证出序列的延迟时间公式及重要性质。并在功耗、面积(资源)占用约束下,优化设计了操作位数复盖范围为10～854位的94个混合模块无等待时间序列超前进位加法器。实现了保持CLA模块速度条件下,最大限度地扩展操作位数的目的。The hybrid modules cascade Carry Lookahead Adders （CLA） without waiting time sequence was advanced on the basis of analysis delay time formula of hybrid modules cascade CLA for the purpose of the fullest expanding operand bit of CLA under conditions of not raising delay time of CLA. The definitions of hybrid modules CLA without waiting time sequence and without waiting time complete sequence were given, and the delay time formula and important properties were deduced. Under constraint of power dissipation and area （resourced） occupation, ninety-four hybrid modules cascade CLA without waiting time sequence, covered area 10 to 854 operand bit, were designed. The purpose of fullest expanding operand bit of CLA was realized on condition that CLA kept speed.

关 键 词：超前进位加法器 混合模块 无等待时间序列 延迟时间公式 操作位数 优化设计 

分 类 号：TP342.21[自动化与计算机技术—计算机系统结构]