数字下变频器的设计与FPGA实现  

A Design of Digital Down Converter and an Implement of it Based on FPGA

作　　者：郭浩[1] 邓建国[1] 董桢[1] 张凡[1] 

机构地区：[1]西安交通大学,陕西西安710049

出　　处：《中国有线电视》2005年第23期2327-2330,共4页China Digital Cable TV

基　　金：国家高技术研究发展计划资助项目(2005AA123910)

摘　　要：数字下变频技术在移动通信、数字广播、电视领域具有重要应用价值,然而专用的数字下变频芯片通常都是针对一定范围内的抽取率设计,因而在通用性强的同时也使得针对性较差,尤其是在较低抽取率情况下由于抽取滤波器的限制使性能恶化,往往需要额外的、较高阶的补偿滤波器才能获得满意效果。针对这一问题,提出一种数字下变频器的FPGA实现方案,该方案针对B3G移动通信系统中一个具体的数字下变频指标要求进行了量体裁衣的设计,实现了高速、高性能的数字下变频。Digital Down Converter （ DDC ） technology plays an important role in the practical fields of mobile communications, digital broadcasting and television. However usually Digital Down Converter chips are designed to adapt to the demand that the abstraction rate should cover a certain range, as a result that the performance of DDC chips are not good especially at a low abstraction rate, although they can be used for different abstraction rates, and an extra compensation filter is required to gain a satisfactory performance. Considering the problem above, a DDC method based on FPGA is put up in this paper, which is designed for the target of a specific DDC application of a B3G mobile communication system. And therefore a DDC with a high speed and a high performance is realized.

关 键 词：数字下变频 FPGA 抽取滤波器 

分 类 号：TN773[电子电信—电路与系统]