一种全差分CMO S采样/保持电路  

A Fully Differential CMOS Sample and Hold Circuit

作　　者：陈海燕[1] 肖坤光[2] 张正璠[2] 周平[1] 张红[1] 

机构地区：[1]重庆邮电学院,重庆400065 [2]中国电子科技集团公司第二十四研究所模拟集成电路国家重点实验室,重庆400060

出　　处：《微电子学》2005年第6期673-676,共4页Microelectronics

摘　　要：文章对影响采样/保持电路精度的电荷注入效应和时钟馈通效应进行了分析,提出了一种全差分CMOS采样/保持电路的设计方案,有效地消除了电荷注入效应误差和时钟馈通误差,极大地减小了其非线性误差,并保证了较高的精度。设计的电路采用TSMC 0.35μm CMOS工艺提供的PDK,在Cadence SpectreS环境下进行仿真验证。测试结果表明,电路信噪比达-81 dB,积分非线性为±0.25 LSB。该电路已运用到一种高速高精度A/D转换器中,性能良好。Charge injection effect and clock feedthrough effect, which affect the precision of sample and hold cir cults, are analyzed. And a total differential CMOS sample and hold circuit is designed, which effectively eliminates both charge injection and clock feedthrough errors, minimizing nonlinearity errors and ensuring a much higher preci sion. Based on TSMC＇s 0.35μm CMOS process, the circuit is simulated using Cadence SpectreS. Test results show that an SNR of -81 dB and an integral nonlinearity of ±0.25 LSB have been achieved for the circuit, which was used in a high speed and high precision A/D converter and excellent performance was achieved.

关 键 词：CMOS 采样/保持放大器 A/D转换器 电荷注入效应 时钟馈通效应 

分 类 号：TN432[电子电信—微电子学与固体电子学]