一种新的SoC流水总线设计及性能分析  

Design and Performance Analysis ofa New SoC Pipelined Bus

作　　者：黄林峰[1] 张志敏[2] 安虹[1] 

机构地区：[1]中国科学技术大学计算机科学技术系,安徽合肥230027 [2]中国科学院计算技术研究所,北京100086

出　　处：《计算机工程与科学》2005年第12期82-83,104,共3页Computer Engineering & Science

基　　金：国家自然科学基金资助项目(60373043);国家863计划资助项目(2002AA1Z1040)

摘　　要：根据SoC系统几种关键因素对总线的影响,本文提出总线性能分析模型用于分析增加流水线级数与提升系统性能之间的关系。利用分析结果,我们设计出一种高效的SoC流水总线。通过与支持同样传输协议的总线的性能比较表明,相对于传统的共享总线,该总线可以节省15%以上的总线时间。该总线已成功地用于一款百万门级32位SoC的设计。The performance of SoC is based on the efficiency of its bus. We propose a bus performance model which demonstrates the relations between the bus performance and several substantial features of a SoC system. We also present carefully the analysis of the impact which is exerted on the bus performances by the improvement of the pipeline stages of a bus. We design an efficient pipelined bus from the analysis results, and compare its efficiency with that of the bus which performs the same transport protocols but do not support the pipeline, and mention one of its implementations on 32-bit SoC with millions of gates.

关 键 词：SOC 流水总线 性能模型 

分 类 号：TP301[自动化与计算机技术—计算机系统结构]