用于高速PLL的CMOS电荷泵电路  

A Novel CMOS Charge-Pump Circuit for High-Speed PLL Application

作　　者：王烜[1] 来金梅[1] 孙承绶[1] 章倩苓[1] 

机构地区：[1]复旦大学专用集成电路与系统国家重点实验室,上海200433

出　　处：《复旦学报（自然科学版）》2005年第6期929-934,共6页Journal of Fudan University：Natural Science

摘　　要：提出了一种应用于高速锁相环中的新型CMOS电荷泵电路.电荷泵核心部分为一带有参考电压电路的双管开关型电路,并对运放构成的反馈回路进行了改进,降低了电荷泵输出电压的抖动.电路采用chartered 0.35 μm 3.3 V CMOS工艺实现,模拟结果表明电流源输出电压在1～3 V区间变化,其输出电流基本无变化,上下电流的失配率小于0.6%,具有很高的匹配性.在3.3 V电源电压下,电荷泵输出电压的范围为0～3.1 V,具有宽摆幅和低抖动(约0.2 mV)等优点,能很好地满足高速锁相环的性能要求.A charge-pump circuit for high-speed PLL application is proposed. The core circuit of the charge-pump consists of two-transistor switches and employs a dummy reference branch, the feedback circuit constituted of an OPA is improved to reduce the spikes of the output voltage. The circuit is designed in 0.35 μm 3.3 V standard CMOS process. Simulation shows that when its output voltage varies from 1 to 3 V the output currents of the current source almost keeps constant, and its currents mismatch is less than 0.6 % showing a good matching performance. This charge-pump has a wide-range output voltage varying from 0 to 3.1 V with a high stabilization. Simulation results show that the circuit is suitable for high-speed PLL＇s applications.

关 键 词：半导体技术 电荷泵 锁相环 鉴频鉴相器 压控振荡器 

分 类 号：TN432[电子电信—微电子学与固体电子学]