用MATLAB在FPGA芯片中实现数字下变频设计  

Realization of Digital Down Conversion in FPGA Chip by Using MATLAB

作　　者：贾雪琴[1] 李强[1] 王旭[1] 李景宏[1] 

机构地区：[1]东北大学信息科学与工程学院,辽宁沈阳110004

出　　处：《计算机仿真》2005年第12期303-306,共4页Computer Simulation

摘　　要：数字下变频在接收系统的数字化和软件化过程中起到了至关重要的作用。该文研究了高倍抽取的数字下变频设计,重点分析了基于级联积分梳状滤波器和级联半带滤波器的多级抽样频率算法。采用最新的设计软件Systemgenerator软件可以方便地在MATLAB中实现算法仿真并可生成FPGA芯片的下载文件,简化了设计流程,降低了开发成本和周期。提出了一种基于计算机ISA总线的系统验证方法。用Systemgenerator设计和仿真基于FPGA芯片的的硬件设计有效地验证了算法并降低了试验成本,是一种好方法。Digital down conversion plays a key role in the digitized and software - oriented process of the receiver system. This paper studies the high decimation ratio of digital down converter,and especially analyzes the multi - stage decimation algorithm based on CIC filter and HB filter. It will reduce the cost and the development time by using the newest Systemgenerator which can simulate the design and download it to FPGA easily. And verifying the design with an ISA bus of computer will save lots of money, effectively. Using MATLAB design and simulation hardware projects based on FPGA is a good method.

关 键 词：数字下变频 半带滤波器 级联积分梳状滤波器 现场可编程门阵列 

分 类 号：TN998[电子电信—信号与信息处理]