一种SoC实现ABME的并行结构分析  

The parallel architecture to achieve ABME in SoC

作　　者：张方[1] 赵波[1] 肖嵩[1] 吴成柯[1] 

机构地区：[1]西安电子科技大学ISN国家重点实验室,陕西西安710049

出　　处：《电路与系统学报》2005年第6期35-39,共5页Journal of Circuits and Systems

基　　金：国家自然科学基金资助项目(60002007)

摘　　要：自适应块大小运动估计(ABME)对于H.264/H.26L的高编码增益具有非常重要的作用,而其复杂的处理算法使其用于实时压缩编码受到很大的限制。本文提出一种在系统芯片(SoC)实现ABME的空间并行结构,其主要思想是将单个16×16宏块的匹配搜索分成并行16个4×4结构的处理单元,所有单元以相同步调同步搜索匹配块并计算每一步的SAD值,接着采用多个独立单元分别计算不同位置、不同数目的4×4子块所拼接成的块(16×8、8×16、8×8等等)对应的SAD及运动矢量MV,从而找出每种块结构所对应的最优匹配位置及匹配误差,编码器采用拉格朗日函数判据从中选择一种块结构作为编码时的运动估计单元。EDA软件仿真验证了本文算法的可行性及有效性。A novel and efficient parallel algorithm and its VLSI architecture are proposed to design adaptive block-size motion estimation （ABME） of H.264/H.26L in System on Chip （SoC）. The 16×16 macro block is divided into sixteen 4×4 sub-blocks and processed separately. Every sub-block searches its match block and SAD is calculated with same step simultaneously, then we can calculate the match error of those blocks with different shapes such as 16×16, 16×8, 8×16, 8×8 in current search coordinates, since they are comprised of sub-blocks with different numbers or positions. Thereby, the motion estimation results of all Nock shapes are obtained, and we choose the one for video coding according to rate-distortion optimization and Lagrangian function. EDA software simulation results show that the parallel algorithm is feasible and efficient to decrease the system complexity and processing delay.

关 键 词：H.264/H.26L 自适应块大小的运动估计(ABME) 在系统芯片(SoC) 

分 类 号：TN919.8[电子电信—通信与信息系统]