32位RISC微处理器“龙腾R2”浮点流水线的设计和实现  

Design and Implementation of the Floating-Point Pipelining in 32-bit RISC Microprocessor "LongTeng R2"

作　　者：李大鹏[1] 张盛兵[1] 罗旻[1] 

机构地区：[1]西北工业大学航空微电子中心,陕西西安710072

出　　处：《微电子学与计算机》2006年第1期188-191,共4页Microelectronics & Computer

基　　金：国防"十五"预研基金项目(41308010108)

摘　　要：文章介绍了32位RISC微处理器“龙腾R2”浮点处理单元的体系结构和设计,重点讨论了乱序执行、乱序结束的高性能浮点流水线设计。为了实现流水线中的精确中断响应,本文采用了一种基于操作数指数和操作类型的浮点异常预测的方法,根据预测结果决定流水线的发射策略。基于0.18ΜM标准单元综合的结果表明:采用该方法实现的浮点处理流水线,与顺序控制和基于TOMASULO算法实现的浮点处理单元相比,整个FPU在付出较少硬件面积的情况下得到了理想的效果,满足功能和时序要求。This thesis proposes the architecture of the floating-point unit in a 32-bit RISC microprocessor ＂LOngTeng R2＂, and emphatically discusses the design and implementation of a high-performance floating-point pipelining with out-of-order execution and out-of-order termination. Aiming at the precise interruption response in floating-point pipelining, we utilize a precise interruption prediction method based on the exponents of operands and the types of operations, by whose predicted results the issue strategy can be determined. Through the simulation and synthesis based on the standard cells of 0.18μm technology, we can conclude that, compared with the floating-point unit with in-order control and Tomasulo Algorithm, this implementation achieves a satisfactory result with a smaller area as well as satisfies all the requirements and specifications of the microprocessor.

关 键 词：浮点单元 异常预测 乱序执行 RISC 

分 类 号：TP39[自动化与计算机技术—计算机应用技术]