基于FPGA的IRIG-B码解码器设计  

Design of IRIG-B Decoder Based on FPGA

作　　者：杨保平 [1] 郭文峰 [2] 卜格鸿 [3] 唐斌 [1] 

机构地区：[1]装备指挥技术学院,研究生部,北京,101416 [2]吉林大学,通信学院,吉林,长春,130012 [3]装备指挥技术学院,电子工程系,北京,101416

出　　处：《装备指挥技术学院学报》2005年第6期79-82,共4页Journal of the Academy of Equipment Command & Technology

基　　金：部委级资助项目

摘　　要：针对FPGA的结构与性能特点,深入分析了以往使用单片机或复杂的可编程逻辑器件(complicated programmable logic device,CPLD)实现IRIG-B码(DC码)解码的优缺点;提出了一种基于现场可编程门阵列(field programmable gate array,FPGA)来实现对B码(DC码)的解码及周期信号输出的新方法;该方法基于一片FPGA芯片,与以往的各种方法相比,具有灵活性、开放性、简单实用、体积小、功耗低的优点,同时提高了同步精度,具有较强的抗干扰性.Aiming at the characteristics of structure and performance of field programmable gate array（FPGA）, several former ways of realizing IRIG-B code （DC code ） using SCM or CPLD（complicated programmable logic device） are discussed. Based on FPGA, a new method of decoding B code （DC code ） and producing periodical signal, is put forward. With one chip and compared with the former methods, the way of decoder realizing has its advantages of flexibility, opening, simpleness, smallness and low consuming. Meanwhile, it enhances the precision of synchronous, as well as the anti-jamming ability.

关 键 词：现场可编程门阵列 靶场间仪器组-B码 解码 同步 

分 类 号：TN915.851[电子电信—通信与信息系统]