基于指令统计的SOPC硬件资源优化技术  

Hardware Resource Optimization Technique of SOPC Based on Instruction Statistics of Application Program

作　　者：李树盛[1] 杨碧波[2] 

机构地区：[1]中北大学教育部仪器科学与动态测试重点实验室,山西太原030051 [2]哈尔滨工业大学,黑龙江哈尔滨150090

出　　处：《中北大学学报（自然科学版）》2005年第6期408-412,共5页Journal of North University of China(Natural Science Edition)

摘　　要：在可编程片上系统(System on P rogramm ab le Ch ip,SOPC)中,特定应用程序中用到的指令是软核CPU指令集的子集,如果在FPGA中实现软核CPU时仅保留应用程序用到的指令子集,将可以提高硬件资源利用率.文中分析了对应用程序进行指令统计的方法,重点介绍了通过修改HDL文件对8051软核CPU指令集进行删减和扩充的技术.采用这一技术设计的SOPC芯片硬件资源利用率得到了显著的提高,降低了系统成本,适用于可编程逻辑资源受到限制和对成本敏感的嵌入式应用中.In any specific application of the system on programmable chip（SOPC）, the instructions used compose a unique subset of the instruction set of the soft-core CPU. The soft-core CPU can be implemented in FPGA with more efficient hardware resource usage if only the subset of the instruction set is implemented. In this paper, a method of applying instruction usage statistics to 8051 MCU based applications is studied. Based on this method, the techniques of both reducing and extending the instruction set of the 8051 soft-core CPU by modifying the VHDL source code are thoroughly studied. An SOPC is built according to this technique and results in more efficient hardware resource usage and reduced system cost. This technique can be applied to resource-limited and cost-sensitive embedded applications.

关 键 词：SOPC 8051单片机 软核CPU 指令统计 指令集删减 指令集扩展 

分 类 号：TP23[自动化与计算机技术—检测技术与自动化装置]