用传输门VCO和动态PFD设计低功耗CMOS琐相环(英文)  

A CMOS Low Power PLL Designed in Transistor Level with Transmission Gate VCO and Dynamic PFD

作　　者：袁寿财[1] 郑月明[1] 

机构地区：[1]西安交通大学电子与信息工程学院电子科学与技术系,西710049

出　　处：《电子器件》2005年第4期775-777,共3页Chinese Journal of Electron Devices

基　　金：西安交通大学在职博士基金项目资助(11217.532)

摘　　要：锁相环(PLL)是VLSI系统的重要单元电路之一,为了实现高速低功耗的CMOS锁相环,用传输门VCO和动态反相器PFD电路设计CMOS锁相环。传输门结构VCO具有高速、低电压和低功耗的特性,而动态反相器PFD具有功耗低和面积小的特点。SPICE模拟表明,当电源电压为2.5V时,基于0.6μmCMOS工艺设计的CMOS锁相环电路,工作频率高达1000MHz,而功耗低于50mW。To realize the high speed and low power CMOS PLL（Phase Locked Loop）, the new circuits of VCO and PFD is designed in transistor level. In the VCO, the high speed and low power is realized using transmission-gate（TG） with an adaptive delay cell and low supply sensitivity. This delay cell has a built-in compensation circuit that senses and corrects the delay variation caused by supply fluctuation. And in the PFD, low power and small chip area is realized with the dynamic inverter. A fully CMOS PLL using these components has been designed based 0. 6μm CMOS technology and its SPICE model. SPICE simulation results show that at 2.5V supply voltage, the designed PLL can operate over 1000 MHz and dissipate power less than 50mW.

关 键 词：传输门 低功耗 CMOS 电路设计 模拟 SPICE 压控震荡器 锁相环 

分 类 号：TN432[电子电信—微电子学与固体电子学]