New method to implement digital down converter in radar system  

作　　者：Ma Zhigang Wen Biyang Zhou Hao Bai Liyun 

机构地区：[1]Radio Propagation Lab, Electronics and informations school, Wuhan Univ., Wuhan 430079, P. R. China

出　　处：《Journal of Systems Engineering and Electronics》2005年第4期775-780,共6页系统工程与电子技术（英文版）

基　　金：Thisprojectwassupportedbythe"863"HighTechnologyDevelopmentProjectofChina(2001AA631050).

摘　　要：Digital down converter （DDC） is the main part of the next generation high frequency （HF） radar. In order to realize the single chip integrations of digital receiver hardware in the next generation HF Radar, a new design for DDC by using FPGA is presented. Some important and practical applications are given in this paper, and the result can prove the validity. Because we can adjust the parameters freely according to our need, the DDC system can be adapted to the next generation HF radar system.Digital down converter （DDC） is the main part of the next generation high frequency （HF） radar. In order to realize the single chip integrations of digital receiver hardware in the next generation HF Radar, a new design for DDC by using FPGA is presented. Some important and practical applications are given in this paper, and the result can prove the validity. Because we can adjust the parameters freely according to our need, the DDC system can be adapted to the next generation HF radar system.

关 键 词：high frequency radar FPGA DDC decimation. 

分 类 号：TN95[电子电信—信号与信息处理]