VHDL延时语句的综合算法研究  

Research on Synthesis Algorithm of Delay Statements in VHDL

作　　者：程利新[1] 石峰[1] 

机构地区：[1]北京理工大学信息科学技术学院计算机科学工程系,北京100081

出　　处：《计算机工程》2006年第4期15-17,38,共4页Computer Engineering

基　　金：国家自然科学基金资助项目(69973007)

摘　　要：为了使得综合系统能够自动综合经设计迭代后由反向标注得到的时序信息,同时提高综合结果与模拟结果的时序一致性,对作为时序信息载体的延时语句的综合方法进行了研究,将延时语句考虑为延时约束,并提出了相应调度模型DTC_DFG及其调度算法。采用启发式机制使得调度算法的解空间搜索过程具有跳出局部最优的能力,此算法可在多项式时间复杂度下得到全局最优调度解。实验结果表明,该调度算法不仅能够有效综合延时语句,使得综合结果能够与模拟结果达到较好的一致,而且提供了一种给出延时约束的方便手段,减少了综合过程中的人工干预,极大地提高了设计效率。This paper researches the synthesis methodology of delay statements for making the backing marked timing information that is gotten from design iteration pass can be automatically synthesized, as well as the timing consistency between synthesis result and simulation result can bc improved, and presents a new scheduling algorithm, This algorithm considers the delay statements as delay time constraints, Scheduling data structure： DTC_DFG（delay time constrainted data flow graph） is constructed and scheduled. A heuristic method is presented for the scheduling algorithm to jump out local optimization and reach global optimization in polynomial time complexity. Experiment results show that delay statements can be efficiently synthesized by the schedulign algorithm presented, at the same time, the synthesis result and simulation result can be more consistent in timing. And a convenient means has been presented to set tinting constraints, thus the manual interuption in synthesis can be decreased; the design efficiency can be improved greatly.

关 键 词：高级综合 解空间 调度 延时约束 

分 类 号：TP311[自动化与计算机技术—计算机软件与理论]