可编程逻辑器件亚稳态的分析与测试  

Metastability of PLDs in Analysis and Test

作　　者：许新新[1] 赵雷[1] 华熹曦[1] 郭琦[1] 霍林[1] 李惠军[1] 

机构地区：[1]山东大学信息科学与工程学院,济南250100

出　　处：《电子质量》2006年第2期3-6,共4页Electronics Quality

摘　　要：随着可编程逻辑器件(PLD)的功能日益强大,工作频率不断提高。由于片上多时钟域系统的集成,使得异步信号数量增加,由此带来了所谓的亚稳态(metastable)问题。亚稳态问题对器件的可靠性将造成严重影响。基于PLD器件亚稳态的成因与机理,本文提出一种简便、可靠的PLD器件亚稳态性能的测试方案。Because PLDs （Programmable Loglo Devloe） are continuously becoming more and more powerful,the maximum operating frequency of the device iS higher. Given multi-clock domain systems integrated In the single chip,the number of asynchronous greatly increased, the metastability has Increasingly Important effects on the rellability of the PLDs.This article discusses the causes of metastable problems In PLDs end presents a rellable end convenient test scheme of PLDs＇metastable performance.

关 键 词：亚稳态 平均无故障时间 测试 可编程逻辑器件 

分 类 号：TN791[电子电信—电路与系统]