集成电路互连线寿命的工艺缺陷影响分析  

Analysis to Interconnect Lifetime Affected by Integrated Circuit Manufacturing Defect

作　　者：赵天绪[1] 段旭朝[1] 郝跃[2] 

机构地区：[1]宝鸡文理学院计算与信息研究所,宝鸡721007 [2]西安电子科技大学微电子所,西安710071

出　　处：《计算机学报》2006年第2期227-232,共6页Chinese Journal of Computers

基　　金：陕西省自然科学基金(2002F30);陕西省教育厅计划项目基金(02Jk194)资助~~

摘　　要：在深亚微米和超深亚微米集成电路中,互连线失效是影响集成电路可靠性的主要因素之一.由于在集成电路制造过程中存在着缺陷,缺陷的出现导致了集成电路可靠性的下降,尤其是出现在互连线上的丢失物缺陷加剧了互连线的电迁移效应,因此电迁移失效依然是其主要的失效模式.文中讨论了电路的互连线的寿命模型,分析了丢失物缺陷以及刻蚀工艺的扰动对互连线宽度的影响,提出了新的互连线寿命估计模型.该模型还考虑了线宽、线长和缺陷峰值粒径等因素对导线寿命的影响.利用该模型可以估算出受丢失物缺陷以及刻蚀工艺扰动影响的互连线的寿命变化情况,这对IC电路设计有一定的指导作用.文中还利用模拟实验证明了该模型的有效性.The failure of interconnect is one of the most important factors affecting IC reliability for deep-sub-micron and super deep-sub micron scale. Since there exist defects in IC manufacturing process,the defects occurring on the chip make IC＇s reliability decreasing. When a missing metal defect appears on interconnect, it makes electromigration effect of interconnect more seri- ous. Therefore, electromigration effect is still a dominating failure mechanism of interconnect. In this paper, the lifetime model of IC interconnect is discussed, the effect of the missing metal de fect and the random disturbance of IC etching process to the width of interconnect is analyzed, and a new estimation model of interconnect lifetime is presented. Many factors, such as the sizes of the defect, wire width, wire length and so on, are considered in this new model. This model can be used to estimate the vary of interconnect lifetime caused by defect and the random disturb ance of IC etching process, which may give directions to IC design. The simulation results show that the model is valid.

关 键 词：互连线寿命 电迁移 工艺扰动 缺陷 

分 类 号：TP301[自动化与计算机技术—计算机系统结构]