可编程浮点数字信号处理器LS-DSP数据路径的设计  

The design of data path for a programmable floating-point Digital Signal Processor LS - DSP

作　　者：车德亮[1] 许琪[1] 沈绪榜[1] 

机构地区：[1]西安微电子技术研究所,陕西西安710054

出　　处：《信号处理》2006年第1期86-90,共5页Journal of Signal Processing

基　　金：国防预研基金资助(41308010203)

摘　　要：LS-DSP是针对航天数字信号处理应用而开发的32位可编程浮点数字信号处理器。本文讨论LS—DSP数据路径的设计,即ALU、乘法器、数据地址产生器三大功能单元的设计。在ALU的设计中,本文采用了一种新的前导0／1判断逻辑结构,其AT2比传统并行方式减少了约15．3％。在乘法器设计中,本文采用了一种新的尾数乘法阵列组织结构,其 AT2比传统的Wallace树结构减少了约12％。为了使LS-DSP更好的支持数字信号处理应用,本文提出了支持顺序、倒位序、循环三种数据寻址计算的数据地址产生器生成算法。LS-DSP现已投片成功,其采用0．5um三层金属布线CMOS工艺制造,面积6．2×6．7mm2,主频为50MHz。LS - DSP is a programmable 32 - bit floating - point Digilal Signal Processor developed for aerospace application. This paper discusses data path design of LS - DSP, which consists of ALU ,Multiplier ,Address Generator. In the design of ALU, a novel architecture of LOD has been put forward, with 15.3% of AT^2 decrement compared with the old parallel LOD architecture. In the design of Multiplier, this paper proposes a new architecture for 24 - bit tree multipliers, and the estimated AT^2 reduction compared with Wallace trees is around 12%. Address Generator algorithm is design for DSP application, which support sequential ,Bit - Reversed and Ci,cular addressing mode conveniently. LS - DSP is fabricated in a 0. 5um three - mental CMOS process, the area is 6.2 × 6.7mm^2 , and the operation frequency is 50MHz.

关 键 词：浮点数字信号处理器 数据路径 ALU 乘法器 数据地址生成器 

分 类 号：TP391[自动化与计算机技术—计算机应用技术] U666.12[自动化与计算机技术—计算机科学与技术]