基于HALO规则的片内信号线寄生电感提取法  

An inductance extraction method for on-chip signal lines based on HALO rules

作　　者：何剑春[1] 贾立新[1] 王涌[1] 

机构地区：[1]浙江工业大学信息工程学院,浙江杭州310032

出　　处：《浙江工业大学学报》2006年第1期86-88,96,共4页Journal of Zhejiang University of Technology

基　　金：浙江省教育厅资助科研项目(20051399)

摘　　要：VDSM工艺下,芯片的高速、高集成度趋势使电磁耦合作用不容忽略;而电感效应的引入则使VLSI设计和验证变得复杂.利用HALO规则划分互连寄生电感交互作用域,将一类基于BP网络的并行导体电感计算方法(NNIE)应用于RLIE的环电感分段计算,提出一种快速获取布置于多层平行电源/地网络内的信号线上频变电感参数的方法.仿真结果表明该方法能有效实现电感参数估计,可作为片上关键线网设计的有效向导.Since VDSM designs tend to be much faster and denser, inductive effect is becoming more and more important. While parasitic inductance of interconnects has to be taken into account, most IC design and verification methodologies are becoming significantly complicated. In this paper, HALO rules are used to divide the chip interconnect into a collection of disjoint horizontal or vertical interaction regions. A quick inductance extraction method based on BP neural networks is presented to calculate loop inductance in the RLIE. Simulation results show that this method can estimate inductance values quickly and efficiently. It can be regarded as one kind of good design guidancc for important nets.

关 键 词：HALO规则 限制回路 频变寄生电感 NNIE 

分 类 号：TN402[电子电信—微电子学与固体电子学]