功能测试矢量的重排与测试时间的压缩  

Test Time Reducing Based on Functional Test Vectors Reordering

作　　者：范志翔[1] 罗岚[1] 陆生礼[1] 

机构地区：[1]东南大学国家专用集成电路系统工程技术研究中心,江苏南京210096

出　　处：《现代电子技术》2006年第5期82-83,89,共3页Modern Electronics Technique

摘　　要：对于集成电路测试而言,测试时间与成本直接相关,减少测试所需的时间意味着测试成本的降低。对于大型的测试矢量集,由于ATE存储器大小的限制,无法一次装载所有的测试矢量,需要多次的loadunload过程,从而浪费了大量的时间。通过测试矢量顺序的优化可以有效地减少重载次数而大大降低测试所需时间。应用模拟退火算法可以对测试矢量顺序进行全局的优化,得到该问题的近似最优解。As far as IC test is concerned,time is a key factor to the cost of test. Especially for some large test vectors,as the limit of the ATE memory, it is impossible to load all test patterns at a time. That means the process of load and unload needs to be repeated many times,it costs a lot of time;so that we need reorder the test vectors to reduce the time of load and unload. In order to get best solution to this problem,simulated annealing is used in this paper to reorder the test vectors from a global point of view.

关 键 词：测试时间 ATE 测试矢量顺序 模拟退失算法 

分 类 号：TN431.2[电子电信—微电子学与固体电子学]