HDTV采用的100MHz 2-D(8×8)DCT/IDCT处理器  

A 100MHz 2- D 8X 8 DCT /IDCT Processor for HDTV Applications

作　　者：A.Madisetti A.N.Willson 孙建京 俞永正 

出　　处：《今日电子》1996年第1期125-132,共8页Electronic Products

摘　　要：文章论述了全数字HDTV使用的DCT/IDCT集成信号处理器的设计。该处理器采用8×8方阵,输入信息为两种,一种是方阵象素扫描信息,一种是可以控制正、逆变换的外部控制信号。DCT象素量化是9 Bit,IDCT是12 Bit。该集成电路采用0.8μm的CMOS工艺制成,由GDT图形专家工具软件进行设计,电路的整体尺寸仅为10mm^2。电路的模拟实验表明其最大输入采样频率为100MHz。This Paper discusses the design of a combined DCT /IDCT CMOS integrated circuit for real time processing of HDTV signals. The processor operates on 8×8 blocks. Inputs include the blocked pixels that are scanned one pixel at a time, and external control signals that control the forward or inverse modes of operation. Input pixels have a precision of 9-b for the DCT and 12-b for the IDCT. The layout has been generated with a0.8μm CMOS library using the Mentor Graphics GDT tools and measures under 10mm2. Critical path simulation indicates a maximum input sample rate of 100 MHz.

关 键 词：高清晰度电视 DCT IDCT 信号处理器 

分 类 号：TN949.17[电子电信—信号与信息处理]