钟控传输门绝热逻辑电路和SRAM的设计  

Design of Clocked Transmission Gate Adiabatic Logic Circuit and SRAM

作　　者：汪鹏君[1] 郁军军[1] 

机构地区：[1]宁波大学电路与系统研究所,浙江宁波315211

出　　处：《电子学报》2006年第2期301-305,共5页Acta Electronica Sinica

基　　金：国家自然科学基金(No.60273093);浙江省自然科学基金(No.Y104135);浙江省留学回国人员科研启动基金

摘　　要：本文利用NMO S管的自举效应设计了一种新的采用二相无交叠功率时钟的绝热逻辑电路———钟控传输门绝热逻辑电路,实现对输出负载全绝热方式充放电.依此进一步设计了一种新型绝热SRAM,从而可以以全绝热方式有效恢复在字线、写位线、敏感放大线及地址译码器上的大开关电容的电荷.最后,在采用TSMC 0.25μm CMO S工艺器件参数情况下,对所设计的绝热SRAM进行HSPC IE模拟,结果表明,此SRAM逻辑功能正确,低功耗特性明显.A new adiabatic logic circuit adopting two-phase non-overlap power clocks-Clocked Transmission Gate Adiabatic Logic circuit was designed by using the bootstrap effect of NMOS transistors, so that it could charge or discharge output loads in a fully adiabatic manner. Based on this circuit, a novel adiabatic SRAM was designed. So it could recover the charge of large switching capacitances on word-lines, write bit-lines, sense amplified lines and address decoders in a fully adiabatic manner. Using the parameters of TSMC 0.25μm CMOS device,the adiabatic SRAM designed was simulated by HSPICE. The simulation results indicate that this SRAM has correct logic function and the character of clearly low power.

关 键 词：钟控传输门绝热逻辑 二相无交叠功率时钟 SRAM设计 低功耗 

分 类 号：TN712[电子电信—电路与系统]