隔N位一抽头的串入并出CCD多抽头延迟线  

Series in/Parallel Out CCD Multi-Tapped Delay Line with a Tap Interval of N-Bit

作　　者：胡世忠[1] 

机构地区：[1]重庆光电技术研究所,重庆永川632163

出　　处：《半导体光电》1990年第2期108-112,共5页Semiconductor Optoelectronics

摘　　要：本文将介绍串入并出抽头延迟线的基本原理、器件结构,特别是抽头与非抽头的时钟电极结构。The principle and device configuration of the series in/parallel out CCD tapped delay line with a tap interval of N-bit are described with the emphasis on the configuretion of tapped and non-tapped clock electrodes.

关 键 词：延迟线 多抽头 CCD 串入并出 

分 类 号：TN812[电子电信—信息与通信工程]