MOSI:一种基于超长指令字处理器的同时多线程微体系结构  

MOSI: A SMT Microarchitecture Based on VLIW Processors

作　　者：万江华[1] 陈书明[1] 

机构地区：[1]国防科学技术大学计算机学院,长沙410073

出　　处：《计算机学报》2006年第3期378-383,共6页Chinese Journal of Computers

基　　金：国家自然科学基金(60473079)资助

摘　　要：描述了一种基于超长指令字处理器的同时多线程微体系结构———MOSI(MultiOp Splitting Issue,多操作①分离发射).MOSI动态地发射同一多操作内的指令,并通过写回缓冲保证计算结果的写回顺序与编译器的视图一致,从而以较小的代价解决了SMT技术中的关键问题.文中详细描述了写回缓冲的结构及算法,给出了多个线程的硬件模型,最后对硬件支持线程的个数及Cache的组织结构进行了讨论.实验结果表明,基于MOSI结构的双线程处理器能够将吞吐率提高40%.Simultaneous Multi-Threading（SMT） technique has become the hot spot in architecture research because it can effectively improve processors＇ throughput with relative smaller cost. On the other hand, Very Long Instruction Word（VLIW） is popular in high performance processor design currently. Obviously, applying SMT technique to VLIW processors is profitable, but the remarkable characteristics of these processors, such as lack of hardware dynamic schedule mechanism, make it difficult to implement. This paper presents a SMT microarchitecture based on VLIW processors, named MOSI（MultiOp Splitting Issue）. MOSI dynamically issues instructions in the same MultiOp, and introduces write-back buffer that writes results into registers according to the supposed order of compiler, so it tackles the crucial problem in SMT technique with minimal cost. This paper describes the write-back buffer＇s detail structure and run-time algorithm, and then shows the hardware models of single thread and overall processor. In the end, the organization of Caches and the preferable thread count（hardware supported） are discussed. The experimental result shows that the dual thread processor based on MOSI microarchitecture improves the total throughput by 40%.

关 键 词：同时多线程 超长指令字 多操作 指令发射 写回缓冲 

分 类 号：TP363[自动化与计算机技术—计算机系统结构]