DSSS接收机中PN码同步的FPGA实现  

PN Synchronization in DSSS Receiver Based on FPGA

作　　者：徐芳[1] 梅晓[1] 李司[1] 

机构地区：[1]北京交通大学现代通信研究所,北京100044

出　　处：《现代电子技术》2006年第6期114-116,共3页Modern Electronics Technique

摘　　要：PN码同步是直接序列扩频通信系统实现正确解调的首要条件,由于发送端和接收端的时钟不同所造成的码片相位偏移将影响到传输数据的正确接收,因此根据PN码良好的自相关特性,提出了一种在基带数字信号处理中基于FPGA的能有效锁定发送端和接收端时钟,实现PN码同步的方案。并结合系统框图具体分析了同步捕获和跟踪中各个模块的功能和实现方法,跟踪模块中涉及到模拟电路部分的也给出了具体的电路设计,最后说明了调试过程中的一些问题及解决技巧。PN synchronization is a principal condition for DSSS demodulator. As a result of the different clock between transmitter and receiver ,the phase offset caused by the difference will affect the validity of the transmission data. According to the good relation feature of PN code,this paper proposes a practical method based on FPGA to lock different clock in transmitter and receiver,and solve PN synchronization in baseband digital signal processing. This paper also analyses the function and implementation of each module in the configuratlon,we also give the circuit design in PN tracking part, finally explains some problems we may face in debugging.

关 键 词：同步捕获 跟踪 模拟PLL FPGA 

分 类 号：TN919.34[电子电信—通信与信息系统]