深亚微米SOC高压缩率EDT设计  

Deep Sub-micro SOC High Compression EDT Design

作　　者：吴赛[1] 薛耀国[1] 王豪才[1] 

机构地区：[1]电子科技大学,四川成都610054

出　　处：《微电子学与计算机》2006年第3期139-142,共4页Microelectronics & Computer

摘　　要：EDT(embeddeddeterministictest)是目前最有效的针对大规模片上系统的嵌入式测试方法,与常规基于ATPG的DFT(DesignForTestability)技术相比较,可以在保持相同缺陷覆盖率的情况下,大幅度降低测试成本,缩短测试时间,EDT的关键技术是解压缩器的算法设计,本文研究基于环形发生器的解压缩器设计,它不会对系统的逻辑核进行任何改动,如插入新的测试点或带来新的逻辑不确定态,可以获得40倍以上的压缩率,而且全部设计是基于标准的扫描/ATPG技术,可以非常方便的在SOC(systemonchip)设计环境中实现。在最后部分,我们研究了采用环形发生器解压缩器,在不同容量的SOC系统的EDT设计结果。Embedded deterministic test （EDT） is the most powerful SOC （System on chip） DFT （Design for test） technology. Compared with traditional ATPG DFT technology, it can reduce manufacturing test cost scan test time to meet same fault coverage. The key technology of EDT is decompressor algorithm design. This paper presents a novel decompressor based on ring generator, which does not require any modifications to the core logic such as the insertion of test points or logic bounding unknown states. The compression rate could be more than 40 times. The presented scheme is widely applicable and easy to deploy because it is based on the standard scan/ATPG methodology and adopts a very simple flow. At the last paragraph, we present the design results of using ring generator decompressor to design EDT for different scale SOC.

关 键 词：微电子技术 嵌入式测试 研究与设计 测试矢量压缩 

分 类 号：TN407[电子电信—微电子学与固体电子学]