一种基于准浮栅技术的超低压折叠运算放大器设计  

Novel Folded Ultra-Low Voltage Op Amp Design Based on Quasi-Floating Gate Transistors

作　　者：张宝君[1] 杨银堂[1] 朱樟明[1] 张海军[1] 

机构地区：[1]西安电子科技大学微电子学院宽禁带半导体材料与器件教育部重点实验室,西安710071

出　　处：《电子器件》2006年第1期33-36,共4页Chinese Journal of Electron Devices

基　　金：国家自然科学基金资助(60476046;90207022);国家部委基金资助(51408010304DZ0140)

摘　　要：介绍了准浮栅晶体管的工作原理、电气特性及其等效电路。提出了一种基于准浮栅技术的折叠差分结构,基于此结构设计,实现了超低压运算放大器。采用TSMC0.25μmCMOS工艺的BSIM3V3模型,对所设计运放的低压特性进行仿真,结果表明,在0.8V电源电压下,运算放大器的直流开环增益为106dB,相位裕度为62°,单位增益带宽为260kHz,功耗仅为3.9μW。The fundamental principle of quasi-floating gate transistors, along with the electrical characteristics and equivalent circuits, are introduced. A new folded differential pair topology based on quasi-fioating gate technique is presented, and an ultra-low voltage op amp based on this structure is designed. By the BSIM3V3 model of TSMC 0.25 μm CMOS process, the low voltage characteristics of the proposed op amp is stimulated, Simulation results indicate that under a single 0. 8 V power supply, the de open-loop gain of the amplifier is 106 dB, the phase margin is 62° and the unit gain band width is 260 kHz with 3. 9 μW power dissipation.

关 键 词：准浮栅 超低压 运算放大器 CMOS 

分 类 号：TN402[电子电信—微电子学与固体电子学]