Response compaction for system-on-a-chip based on advanced convolutional codes  

作　　者：HAN Yinhe LI Huawei LI Xiaowei ANSHUMAN Chandra 

机构地区：[1]Institute of Computing Technology, Chinese Academy of Sciences, Beijing 100080, China [2]Graduate University of Chinese Academy of Sciences-Beijing 100039,China [3]Synopsys, Inc., 700 E.Middlefield Rd.,Mountain view,CA94043,USA

出　　处：《Science in China(Series F)》2006年第2期262-272,共11页中国科学（F辑英文版）

基　　金：supported in part by the National Basic Research Program of China(973)(Grant Nos.2005CB321604 and 2005CB321605);in part by the National Natural Science Foundation of China(Grant Nos.90207002 and 60576031).

摘　　要：This paper addresses the problem of test response compaction. In order to maximize compaction ratio, a single-output compactor based on a （n, n-1, m, 3） convolutional code is presented. When the proposed theorems are satisfied, the compactor can avoid two and any odd erroneous bits cancellations, and handle one unknown bit （X bit）. When the X bits in response are clustered, multiple-weight check matrix design algorithm can be used to reduce the effect of massive X bits. Some extended experimental results show that the proposed encoder has an acceptable-level X tolerant capacity and low error cancellations probability.This paper addresses the problem of test response compaction. In order to maximize compaction ratio, a single-output compactor based on a （n, n-1, m, 3） convolutional code is presented. When the proposed theorems are satisfied, the compactor can avoid two and any odd erroneous bits cancellations, and handle one unknown bit （X bit）. When the X bits in response are clustered, multiple-weight check matrix design algorithm can be used to reduce the effect of massive X bits. Some extended experimental results show that the proposed encoder has an acceptable-level X tolerant capacity and low error cancellations probability.

关 键 词：SOC test response compaction convolutional code ALIASING X bits masking. 

分 类 号：TP301[自动化与计算机技术—计算机系统结构]