数字下变频的FPGA实现  

Realization of Digital Down Conversion by FPGA

作　　者：贾雪琴[1] 李强[1] 王旭[1] 李景宏[1] 

机构地区：[1]东北大学信息科学与工程学院,辽宁沈阳110004

出　　处：《仪表技术与传感器》2006年第1期56-58,共3页Instrument Technique and Sensor

摘　　要：研究了高倍抽取的数字下变频设计,重点分析了基于级联积分梳状滤波器和级联半带滤波器的多级抽样频率算法。并提出了用最新的Systemgenerator软件实现FPGA的设计、仿真方案,缩短了开发周期,简化了设计流程,增加了系统的集成度和稳定性,降低了开发成本。对于混频器、级联积分梳状滤波器和数字下变频器都给出了仿真波形。Studied high decimation ratio of digital down converter, and especially analyzed multi-stage decimation algorithm based on cascaded integrator-comb （CIC） filter and half band （HB）filter. Software, Systemgenerator realized the design and simulating of FPGA （field programmnable gate array）. Projects based on FPGA will afford more stability and more integration for the system, and will reduce the cost and the exploitation-time of the system. The simulation wave of mixer, CIC filter and DDC were all shown.

关 键 词：数字下变频 软件无线电 半带滤波器 级联积分梳状滤波器 FPGA 

分 类 号：TN77[电子电信—电路与系统]