基于门控时钟的寄存器传输级功耗优化  

Low Power Design in the MPCP Module

作　　者：郑国鹏[1] 陈光化[1] 

机构地区：[1]上海大学微电子研发中心

出　　处：《电子技术（上海）》2006年第4期58-60,共3页Electronic Technology

摘　　要：随着深亚微米技术的发展,功耗已经成为现代超大规模集成电路设计中的一个主要设计约束。采用插入门控时钟这一技术对芯片的功耗进行优化,针对插入门控时钟造成的可测性、时序等方面的问题进行详细分析,得到相应的解决办法。最后,使用SMIC的0.25μmCMOS工艺库,并用Synopsys的powercomplier进行功耗优化,可以达到很好的效果。With the development of the deep sub-micron technology,the power consumption of the integrated circuit (IC) has become a dominant design constraint in modern VLSI design. In this paper, the methodology of clock gating is presented to decrease the power consumption. Based on the design of MPCP module, aiming at the issue that clock-gating register is difficult to control during the test, inserting control point before or after the clock-gating latch is used to solve the negative effect of clock gating. Finally, implementing the power optimization by means of Power Compiler, a satisfying result is reached using the SMIC 0.25 um CMOS process.

关 键 词：功耗优化 门控时钟 寄存器传输级 深亚微米技术 集成电路设计 power 设计约束 超大规模 CMOS 可测性 

分 类 号：TN432[电子电信—微电子学与固体电子学] TN402