基于FPGA/CPLD的占空比为1∶n的n分频器的设计  

Design of n Frequency Divider Whose Duty Ratio is 1∶n Based on FPGA/CPLD

作　　者：何静[1] 李清峰[1] 

机构地区：[1]湖南商学院,湖南长沙410205

出　　处：《现代电子技术》2006年第8期17-18,共2页Modern Electronics Technique

基　　金：湖南省自然科学基金项目(04JJ40048)资助

摘　　要：CPLD和FPGA都是可编程逻辑器件,利用他们进行数字系统设计具有设计开发周期短、设计制造成本低、开发工具先进、标准产品无需测试、质量稳定以及实时在线检验等优点。Verilog HDL是目前应用最为广泛的硬件描述语言之一,可以用来进行各种层次的逻辑设计,也可以进行数字系统的逻辑综合、仿真验证和时序分析。简要介绍了CPLD/FPGA器件的特点和应用范围,并以占空比为1∶5的5分频器的设计为例,介绍了在Max+Plus II开发软件下,利用Verilog HDL硬件描述语言设计数字逻辑电路的过程和方法,最后给出了仿真波形。CPLD and FPGA are programmable logic devices. Digital systems designed by them have following merits： short development cycle, low cost of design and manufacture, advanced development tool, bulk article no testing, stable quality and on - line verify. Verilog HDL is a widely used hardware description language, which can be used to do various levels design, logical synthesis, simulation and timing analysis. The paper introduces characteristics and ranges of application of CPLD/ FPGA,and the design process and methods of digital logical circuits with Verilog HDL under Max-k-Plus Ⅱ development software by taken as an example of a 5 frequency divider whose duty ratio is 1 ： 5. At last gives simulation waveform.

关 键 词：Verilog HDL CPLD/FPGA数字逻辑电路设计 占空比 n分频器 

分 类 号：TN772[电子电信—电路与系统]