基于分布式算法的高阶FIR滤波器及其FPGA实现  

High Order FIR Filter Based on Distributed Arithmetic and Its FPGA Implementation

作　　者：朱冰莲[1] 程联营[1] 孔杰[1] 

机构地区：[1]重庆大学通信工程学院,重庆400044

出　　处：《电讯技术》2006年第2期82-85,共4页Telecommunication Engineering

基　　金：重庆市科委应用基础科技项目(7964)

摘　　要：随着FPGA技术的稳步提高,FPGA替代其他技术用于实现高速信号处理已经变得切实可行。针对高阶FIR滤波器十分消耗FPGA硬件资源的问题,提出了一种采用基于位级联的多查找表分布式算法,并以一个32阶8位低通FIR滤波器为例,验证了所提出的方法。仿真结果表明,采用这种方法大大减少了FPGA硬件资源的耗费。As Field Programmable Gate Array（FPGA） technology has been steadily improved, FPGAs are now viable alternatives to other technology implementations for high - speed classes of digital signal processing（DSP） apphcation. To solve the problem that implementation of high order FIR filter consumes rather more hardware resources in FPGA, the bit - serial distributed arithmetic based on multiple look - up tables is presented. A 32 - tap 8 - bit order low pass FIR filter is taken as an example to illustrate the method. Simulation shows that the method saves much more resources in FPGA, and improves the performance of FIR filter to some extent.

关 键 词：数字信号处理 FIR数字滤波器 分布式算法 FPGA 查找表 

分 类 号：TN713[电子电信—电路与系统]