一种新型的四阶低抖动带双控制环路CMOS锁相环  

A New 4th Order and Low Jitter CMOS Phase Locked Loop with a Dual Control Path

作　　者：房华[1] 方厚辉[1] 华孝泉[1] 张杰[1] 庞海珑[2] 

机构地区：[1]湖南大学电气与信息工程学院,长沙410082 [2]上海大学电气院,上海200072

出　　处：《电讯技术》2006年第2期139-143,共5页Telecommunication Engineering

摘　　要：设计了一种四阶低抖动带双控制环路压控振荡器的锁相环(PLL)。该锁相环在恒定的反馈参数下,压控振荡器压频增益几近恒定。锁相环的所有部件都设计在同一芯片上,电路设计基于0.35μmCMOS工艺。HSPICE仿真结果显示,所设计的锁相环路具有很好的抗噪声性能,工作在800MHz频率范围内,整个相位抖动小于4psrms。A low jitter phase -locked -loop（PLL） with 4th order control path is described, and the PLL exhibits improved noise immunity with a wide VCO frequency range. All of the components of the PLL are integrated on one chip. The circuit design is based on 0.35 μm CMOS technology. HSPICE simulation shows at 800MHz operating frequency, the phase noise exhibits less than 4ps rms accumulated jitter.

关 键 词：锁相环 压拉振荡器 CMOS 

分 类 号：TN752[电子电信—电路与系统]