大规模阵列信号处理机的FPGA设计  

The FPGA Design of Large Scale Array Signal Processor

作　　者：江鹏[1] 何国建[1] 蔡惠智[1] 季晓燕[2] 

机构地区：[1]中国科学院声学研究所,北京100080 [2]中船重工717研究所,武汉430074

出　　处：《计算机工程》2006年第8期252-254,共3页Computer Engineering

摘　　要：在雷达和声纳系统中,需要进行非常复杂的数据处理。目前解决这些问题的有效办法是将多个DSP组成阵列处理系统,以增加整体数据处理能力。针对系统的要求,采用基于CPCI的高速阵列信号处理板卡。该板选用AD公司的高性能浮点DSP处理器TigerSharc101,使整板具有14.4GFLOPS的峰值浮点运算能力,它提供Link Port来实现片间和板间通信。该文介绍了该板的原理框图,FPGA的实现结构,着重于Host接口逻辑设计。实践证明,该板具有了超强的运算能力,良好的扩展性。In the modem communication, sonar and radar systems, it needs to process huge data. One of the effective ways to solve this problem is to build a system with multiprocessor, so it can enhance the processing ability. According to the demands of the system, this paper designs a high speed array signal processing board which is based on CPCI structure. It chooses the TigerSharc101 as the core processor, the peak processing ability of the board is 14.4GFLOPS. The board has link ports to realize the communication between TS101 and boards, This paper introduces the base structure of the board and FPGA design and emphasizes on the host interface design. These applications show that the board has a great processing ability and expansibility.

关 键 词：CPCI总线 阵列信号处理 TigerSharc101 

分 类 号：TP316.3[自动化与计算机技术—计算机软件与理论]