基于CMOS工艺的622 MHz电荷泵锁相环设计  

622 MHz Charge Pump PLL Design Based on CMOS Technics

作　　者：窦建华[1] 张锋[1] 潘敏[1] 

机构地区：[1]合肥工业大学计算机与信息学院,安徽合肥230009

出　　处：《现代电子技术》2006年第9期75-77,共3页Modern Electronics Technique

摘　　要：设计了由饱和区MOS电容调谐的环形压控振荡器(RVCO),并将其用于电荷泵锁相环(CPPLL)电路,其中电荷泵部分采用了能消除过冲注入电流的新型电荷泵电路,并采用SmartSpice软件和0.6μm混合信号的CMOS工艺参数进行了仿真。仿真结果表明,此锁相环的锁定时间为5.2μs,锁定范围约为100 MHz,输出中心频率622 MHz的最大周对周抖动为71ps,功耗为198 mW。此电荷泵锁相环电路可以应用于STM 1和STM 4两个速率级别的同步数字体系(SDH)系统。This paper presents a ring voltage- controlled oscillator via MOS capacitance of saturation region tuning, and applies it to a CPPLL circuit, among which the charge pump portion adopts a novel charge pump circuit that can eliminate the overshoot injection current. We have made a simulation using the software SmartSpice and 0.6 μm mixed signal CMOS techniques parameter. The results show that the locked time of the proposed PLL is 5.2 μs, the locked range is about 100 MHz,the cycle - to - cycle jitter of the output center frequency at 622 MHz is 71ps,and its power dissipation is 198 roW. This CPPLL may be applied to two velocity levels SDH system of STM - i and STM - 4.

关 键 词：锁相环 电荷泵 环形压控振荡器 锁定范围 

分 类 号：TN752[电子电信—电路与系统]