一种高效流水低存储的JPEG2000编码芯片设计  

An Efficient Pipeline Design of JPEG2000 Encoder with Low Memory

作　　者：梅魁志[1] 郑南宁[1] 刘跃虎[1] 姚霁[1] 黄宇[1] 王勇[1] 

机构地区：[1]西安交通大学人工智能与机器人研究所,西安710049

出　　处：《电子与信息学报》2006年第4期741-746,共6页Journal of Electronics & Information Technology

基　　金：国家自然科学基金创新群体研究(60021302);国家高技术研究发展计划(2005AA1Z1272)资助课题

摘　　要：该文提出了一种高效流水低存储的JPEG2000编码芯片的设计方案。该方案通过采用双缓存的小波系数存储结构,预速率控制方法,Tier2中的RD斜率值的字节表示,以减少片上存储器;对离散小波变换,算术编码和位平面编码使用高度并行流水等设计结构以提高编码单元电路速度;字节地址空间的RD斜率值搜索提高了Tier2的打包速度;对系统实现中的时钟分配,色度转换,帧存储器控制进行了优化设计。基于该设计方案的整个编码芯片已通过FPGA验证,主要性能参数:小波类型为5／3,支持最大Tile为256×256,最大图像4096×4096,码块为32×32,系统采样率在Tier1工作时钟为100MHz时可达45Msamples／s,压缩图像与JASPER 在压缩20倍时相比均小于0．5dB,在SMIC．25库综合下,等效门为10．9万,片上RAM为862kb。An efficient JPEG2000 encoder is proposed and implemented with high pipeline and low memory architecture. Dual buffers to save the wavelet coefficients, pre-rate allocation and byte expression for Rate-Distortion （RD） slope are used to reduce on-chip memory size. Pipeline and parallel architecture is used in Discrete Wavelet Transform （DWT）, Bit-Plane Encoder （BPE） and Arithmetic Encoder （AE） to increase the part circuit＇s encoding speed, searching the truncated RD slope in byte address space increases the packet formatting speed of Tier2. Problems met in system implementation such as clock distribution, SDRAM control of frame buffer and chrominance-transformation are also designed with optimization. The encoder is verified on FPGA platform. Performance of the encoder is as follows： the size of tile is up to 256×256 with code block in size of 32×32, input sampling rate is up to 45Msamples/s when Tierl is working at the clock of 100 MHz, difference of the PSNR of images compressed by the proposed encoder and JASPER is less than 0.5dB at the rate of 0.4 bit per sample （bps）. Equivalent gates synthesized are about 109k and on-chip RAM is 862kb.

关 键 词：JPEG2000 离散小波变换 算术编码 位平面编码 Tier2 FPGA 

分 类 号：TN492[电子电信—微电子学与固体电子学]