基于FPGA双机容错系统的设计与实现  

Design and implementation of the dual fault-tolerant system based on the FPGA

作　　者：黄影[1] 张春元[1] 刘东[1] 

机构地区：[1]国防科技大学计算机学院,长沙410073

出　　处：《深圳大学学报（理工版）》2006年第2期112-116,共5页Journal of Shenzhen University(Science and Engineering)

基　　金：国家重点基础研究发展计划项目(5131202-3)

摘　　要：根据双机容错技术常用方案及特点,结合现场可编程逻门电路(FPGA)程的特性及相关技术,提出并实现了基于FPGA双机容错系统的设计方案.仲裁器机制根据双机工作的监测信号负责完成主备机切换功能.系统在实现过程中,利用FPGA内部时钟信号clk“同步化”异步信号,不但充分发挥了FPGA的内部资源,且避免了因信号毛刺可能产生的电路错误.仿真结果表明,该双机容错机制的设计方案能完成系统所需功能,可靠性较好.Dual fault-tolerant technique, a key technique to improve reliability of computer system, is widely applied in the design and development of embedded system. Based on various methods in common use and combined with correlative techniques of programmable devices, a scheme of the dual fault-tolerant system based on FPGA is presented. The arbitrator mechanism is important for the real implementation because it supervises the switches between the host and the backup machine. In the process of implementation, not only FPGA＇s inner resources were fully made use of, but also the circuit mistakes caused by signals＇ burrs were avoided using FPGA＇s inner clock signal to make the asynchronous signals synchronized. The simulational result shows good performance.

关 键 词：双机容错 温备 现场可编程逻门电路 

分 类 号：TP302.8[自动化与计算机技术—计算机系统结构]