基为16的高速Montgomery模乘法器VLSI设计  

High-speed radix-16 design of a scalable Montgomery multiplier

作　　者：范益波[1] 曾晓洋[1] 于宇[1] 

机构地区：[1]复旦大学专用集成电路与系统国家重点实验室,上海200433

出　　处：《通信学报》2006年第4期107-113,共7页Journal on Communications

基　　金：国家高技术研究发展计划("863"计划)基金资助项目(2003AA1Z1270);上海市科委重大攻关基金资助项目(03dz15001)~~

摘　　要：针对Tenca-Todorov-Ko?提出的基为8,按字运算的Montgomery乘法器提出了一种改进方案。该方案在不增加硬件开销的基础上采用基为16的设计,相比Tenca-Todorov-Ko?的设计,平均性能提高26%。同时,在硬件上一方面通过调整数据通路以缩短关键路径延迟,达到时钟频率的提升;另一方面,在FIFO设计中对输入数据进行预处理,最终能节省一半的存储器开销。改进后的设计能应用于各种长度的模乘运算和RSA加密。最后,采用上述设计思想,基于0.25μmCMOS标准单元工艺,设计了一款2048bit的RSA测试芯片。该芯片在125MHz的时钟频率下做一次2048bit模幂的时间为28ms。An improved version of Montgomery multiplier was proposed basing the Tenca-Todorov-Koc＇s word based radix-8 Montgomery multiplier. Radix-16 was used for fast without adding any hardware, and the performance was improved up to 26% comparing to the Tenca-Todorov-Koc＇s design. On one hand, shorter critical path and faster frequency were got through adjusting the data-path, on the other hand, a half memory cost by preprocessing the data was saved- which would be stored in FIFO. The improved design was scalable to do any precision modular multiplication and RSA encryption. At last, a 2048-bit RSA test chip was implemented using 0.25 μm technology CMOS standard cell. The chip performs 2048-bit modular exponentiation in 28ms under 125MHz clock period.

关 键 词：信息安全 高速Montgomery乘法器 VLSI 密码算法 

分 类 号：TP309.7[自动化与计算机技术—计算机系统结构]