BESIII主触发系统VME机箱快控制插件的设计  

Design of VME Crate Fast Control Board for BESIII Main Trigger System

作　　者：司孝平[1] 赵棣新[2] 刘振安[2] 

机构地区：[1]华北水利水电学院,河南郑州450011 [2]中科院高能所,北京100039

出　　处：《佳木斯大学学报（自然科学版）》2006年第2期238-241,共4页Journal of Jiamusi University：Natural Science Edition

摘　　要：提出了“可预置计数限的计数逻辑”和“有暂停控制的双向计数器逻辑”,解决了VME总线主板所能处理的中断的频率与输入信号脉冲的频率不匹配的难题,消除了某些信号与系统时钟异步造成的准稳态;所设计的插件实现了VME总线程控流水线式发中断的功能.This paper introduces both ＂the counting logic with loadable port＂ and ＂ the dual direction counting logic with pause port＂ , which resolves the puzzle that the frequency of the interrupt dealed with by the VME master card couldn＇ t match with that of the input signal pulse, and will avoid the uncertain state caused by the asynchronicm beteen some signals and the system clock signal. The board we designed can send out interrupt request to the VME master under Control of the programs.

关 键 词：VME总线 FPGA 仿真 

分 类 号：TP303.2[自动化与计算机技术—计算机系统结构]