高速交替/并行数据采集系统时钟研究  

Clock study of high speed interleaving/multiplexing data-acquisition system

作　　者：张俊杰[1] 武杰[1] 刘尉悦[1] 乔崇[1] 王砚方[1] 

机构地区：[1]中国科学技术大学近代物理系快电子学实验室,安徽合肥230026

出　　处：《中国科学技术大学学报》2006年第3期281-284,共4页JUSTC

基　　金：国家自然科学基金(10505020)资助

摘　　要：研究了交替/并行数据采集系统中采样时钟抖动、采样时钟偏差、高速ADC量化误差与采集系统信噪比的关系.通过对采样数据的一级近似以及合理的假设,推导出了信噪比的数学表达式.用建立的仿真模型验证了数学表达式.结果表明,在输入信号频率较高时,信噪比以20 dB/10倍频下降,时钟抖动等效均方值决定了20 dB/10倍频下降的起始位置.Clock related issues in interleaving/multiplexing data acquisition systems were studied. Based on a linear approximation and some reasonable propositions, a powerful expression for the SNR was derived. A simulation model used to verify the SNR expression was proposed. It is shown that SNR drops 20dB per decade change of signal frequency at high frequency and the equivalent deviation of clock jitter decides the start position where SNR drops.

关 键 词：交替/并行采集 时钟抖动 信噪比 时钟偏差 

分 类 号：TP274.2[自动化与计算机技术—检测技术与自动化装置]