基于FPGA的DVB-T信道内编码和内交织的设计和实现  

The Design and Implementation of DVB-T Channel Inner Coding and Inner Interleaving Based on FPGA

作　　者：李冬梅[1] 张申科[1] 

机构地区：[1]同济大学,上海200433

出　　处：《中国有线电视》2006年第7期667-669,共3页China Digital Cable TV

摘　　要：介绍了地面数字电视广播(DVB-T)发射端的内编码和内交织的硬件实现。经过多次优化设计,使整个DVB-T发射端信道内码消耗资源很少。Hardware implementation of inner coding and inner interleaving at the transmitter end of terrestrial digital video broadcasting （ DVB - T） are introduced. Many times of optimization design makes the channel inner coding at the DVB -T transmitter end consume very little resource.

关 键 词：地面数字电视广播 内编码 内交织 现场可编程门阵列 

分 类 号：TN948.53[电子电信—信号与信息处理]